CFG_RETIME_TX=B_0x0, CFG_RETIME_RX=B_0x0, SDFBCLK_180=B_0x0
SYSCFG FMC retiming logic control register
| CFG_RETIME_RX | Retiming on Rx path 0 (B_0x0): No retiming on Rx path 1 (B_0x1): Retiming on Rx path |
| CFG_RETIME_TX | Retiming on Tx path 0 (B_0x0): No retiming on Tx path 1 (B_0x1): Retiming on Tx path |
| SDFBCLK_180 | Delay on feedback clock 0 (B_0x0): No delay on the feedback clock 1 (B_0x1): Half a cycle delay on the feedback clock |