USB2_EARLY_WR_RSP_ENABLE=B_0x0, SDMMC1_EARLY_WR_RSP_ENABLE=B_0x0, USB1_EARLY_WR_RSP_ENABLE=B_0x0, SDMMC2_EARLY_WR_RSP_ENABLE=B_0x0
SYSCFG AHB-AXI bridge early write response control register
| SDMMC1_EARLY_WR_RSP_ENABLE | None 0 (B_0x0): Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction. 1 (B_0x1): Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response. |
| SDMMC2_EARLY_WR_RSP_ENABLE | None 0 (B_0x0): Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction. 1 (B_0x1): Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response. |
| USB1_EARLY_WR_RSP_ENABLE | None 0 (B_0x0): Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction. 1 (B_0x1): Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response. |
| USB2_EARLY_WR_RSP_ENABLE | None 0 (B_0x0): Early-write response disabled. The last AHB write data beat receives the AXI buffered response for the complete AHB transaction. 1 (B_0x1): Early-write response enabled. AHB-Lite write data beats receive an automatic OK response from the AHB-to-AXI bridge, whatever the B-channel AXI response. |