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stm32 /stm32n6 /STM32N657 /SYSCFG /SYSCFG_VDDIOCCCR

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Interpret as SYSCFG_VDDIOCCCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RANSRC0RAPSRC0 (B_0x0)EN 0 (B_0x0)CS

CS=B_0x0, EN=B_0x0

Description

SYSCFG VDDIO compensation cell control register

Fields

RANSRC

These bits are written by software to define an I/O compensation code for NMOS transistors. This code is applied to the I/O compensation cell when CS = 1.
RAPSRC

These bits are written by software to define an I/O compensation code for PMOS transistors. This code is applied to the I/O compensation cell when CS = 1.
EN

Enables the compensation cell of I/Os supplied by VDDIO.

0 (B_0x0): VDDIO I/O compensation cell disabled

1 (B_0x1): VDDIO I/O compensation cell enabled
CS

Selects the code to be applied for the compensation cell of I/Os supplied by VDDIO.

0 (B_0x0): VDDIO I/O code from the cell (available in the SYSCFG_VDDIOCCSR)

1 (B_0x1): VDDIO I/O code from RANSRC[3:0] and RAPSRC[3:0]

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32