MOE=B_0x0, LOCK=B_0x0, BKE=B_0x0, BKBID=B_0x0, AOE=B_0x0, BKP=B_0x0, BKF=B_0x0, OSSR=B_0x0, BKDSRM=B_0x0, OSSI=B_0x0
TIM16 break and dead-time register
| DTG | Dead-time generator setup |
| LOCK | Lock configuration 0 (B_0x0): LOCK OFF - No bit is write protected 1 (B_0x1): LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. 2 (B_0x2): LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 3 (B_0x3): LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. |
| OSSI | Off-state selection for Idle mode 0 (B_0x0): When inactive, tim_oc1/tim_oc1n outputs are disabled (tim_oc1/tim_oc1n enable output signal=0) 1 (B_0x1): When inactive, tim_oc1/tim_oc1n outputs are forced first with their idle level as soon as CC1E=1 or CC1NE=1. tim_oc1/tim_oc1n enable output signal=1) |
| OSSR | Off-state selection for Run mode 0 (B_0x0): When inactive, tim_oc1/tim_oc1n outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state) 1 (B_0x1): When inactive, tim_oc1/tim_oc1n outputs are enabled with their inactive level as soon as CC1E=1 or CC1NE=1 (the output is still controlled by the timer). |
| BKE | Break enable 0 (B_0x0): Break inputs (tim_brk and tim_sys_brk event) disabled |
| BKP | Break polarity 0 (B_0x0): Break input tim_brk is active low 1 (B_0x1): Break input tim_brk is active high |
| AOE | Automatic output enable 0 (B_0x0): MOE can be set only by software 1 (B_0x1): MOE can be set by software or automatically at the next update event (if the tim_brk input is not active) |
| MOE | Main output enable 0 (B_0x0): tim_oc1 and tim_oc1n outputs are disabled or forced to idle state depending on the OSSI bit. 1 (B_0x1): tim_oc1 and tim_oc1n outputs are enabled if their respective enable bits are set (CC1E, CC1NE in TIMx_CCER register) |
| BKF | Break filter 0 (B_0x0): No filter, tim_brk acts asynchronously 1 (B_0x1): fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2 2 (B_0x2): fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4 3 (B_0x3): fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8 4 (B_0x4): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6 5 (B_0x5): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8 6 (B_0x6): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6 7 (B_0x7): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8 8 (B_0x8): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6 9 (B_0x9): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8 10 (B_0xA): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5 11 (B_0xB): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6 12 (B_0xC): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8 13 (B_0xD): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5 14 (B_0xE): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6 15 (B_0xF): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8 |
| BKDSRM | Break Disarm 0 (B_0x0): Break input tim_brk is armed 1 (B_0x1): Break input tim_brk is disarmed |
| BKBID | Break Bidirectional 0 (B_0x0): Break input tim_brk in input mode 1 (B_0x1): Break input tim_brk in bidirectional mode |