OC3M=B_0x0, CC4S=B_0x0, CC3S=B_0x0
TIM8 capture/compare mode register 2 [alternate]
| CC3S | Capture/compare 3 selection 0 (B_0x0): CC3 channel is configured as output 1 (B_0x1): CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 2 (B_0x2): CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 3 (B_0x3): CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) |
| OC3FE | Output compare 3 fast enable |
| OC3PE | Output compare 3 preload enable |
| OC3M | OC3M[2:0]: Output compare 3 mode 0 (B_0x0): Frozen - The comparison between the output compare register TIMx_CCR3 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 1 (B_0x1): Set channel 3 to active level on match. tim_oc3ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3). 2 (B_0x2): Set channel 3 to inactive level on match. tim_oc3ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3). 3 (B_0x3): Toggle - tim_oc3ref toggles when TIMx_CNT=TIMx_CCR3. 4 (B_0x4): Force inactive level - tim_oc3ref is forced low. 5 (B_0x5): Force active level - tim_oc3ref is forced high. 6 (B_0x6): PWM mode 1 - In upcounting, channel 3 is active as long as TIMx_CNTless thanTIMx_CCR3 else inactive. In downcounting, channel 3 is inactive (tim_oc3ref=0’) as long as TIMx_CNT>TIMx_CCR3 else active (tim_oc3ref=‘1’). 7 (B_0x7): PWM mode 2 - In upcounting, channel 3 is inactive as long as TIMx_CNTless thanTIMx_CCR3 else active. In downcounting, channel 3 is active as long as TIMx_CNT>TIMx_CCR3 else inactive. |
| OC3CE | Output compare 3 clear enable |
| CC4S | Capture/compare 4 selection 0 (B_0x0): CC4 channel is configured as output 1 (B_0x1): CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 2 (B_0x2): CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 3 (B_0x3): CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) |
| OC4FE | Output compare 4 fast enable |
| OC4PE | Output compare 4 preload enable |
| OC4M | OC4M[2:0]: Output compare 4 mode |
| OC4CE | Output compare 4 clear enable |
| OC3M_1 | OC3M[3] |
| OC4M_1 | OC4M[3] |