Regviz

stm32 /stm32n6 /STM32N657 /VENC /VENC_SWREG231

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Interpret as VENC_SWREG231

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SWREG_FIELD

Description

VENC base address for output of down-scaled encoder image in YUYV 4:2:2 format register

Fields

SWREG_FIELD

Base address for output of down-scaled encoder image in YUYV 4:2:2 format (all format mode)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32