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stm32 /stm32u0 /STM32U073 /TIM16 /TIM16_TISEL

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Interpret as TIM16_TISEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TI1SEL

TI1SEL=B_0x0

Description

TIM16 input selection register

Fields

TI1SEL

selects TI1[0] to TI1[15] input

0 (B_0x0): TIM16_CH1 input

1 (B_0x1): LSI

2 (B_0x2): LSE

3 (B_0x3): RTC wakeup

4 (B_0x4): MCO2

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32