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stm32 /stm32u0 /STM32U073 /TIM3 /TIM3_CCER

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Interpret as TIM3_CCER

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15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CC1E 0 (B_0x0)CC1P 0 (CC1NP)CC1NP 0 (CC2E)CC2E 0 (CC2P)CC2P 0 (CC2NP)CC2NP 0 (CC3E)CC3E 0 (CC3P)CC3P 0 (CC3NP)CC3NP 0 (CC4E)CC4E 0 (CC4P)CC4P 0 (CC4NP)CC4NP

CC1P=B_0x0, CC1E=B_0x0

Description

TIM3 capture/compare enable register

Fields

CC1E

Capture/Compare 1 output enable.

0 (B_0x0): Capture mode disabled / OC1 is not active

1 (B_0x1): Capture mode enabled / OC1 signal is output on the corresponding output pin
CC1P

Capture/Compare 1 output Polarity.

0 (B_0x0): OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)

1 (B_0x1): OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
CC1NP

Capture/Compare 1 output Polarity.
CC2E

Capture/Compare 2 output enable.
CC2P

Capture/Compare 2 output Polarity.
CC2NP

Capture/Compare 2 output Polarity.
CC3E

Capture/Compare 3 output enable.
CC3P

Capture/Compare 3 output Polarity.
CC3NP

Capture/Compare 3 output Polarity.
CC4E

Capture/Compare 4 output enable.
CC4P

Capture/Compare 4 output Polarity.
CC4NP

Capture/Compare 4 output Polarity.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32