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stm32 /stm32u0 /STM32U073 /TIM3 /TIM3_DCR

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Interpret as TIM3_DCR

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15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DBA0 (B_0x0)DBL

DBA=B_0x0, DBL=B_0x0

Description

TIM3 DMA control register

Fields

DBA

DMA base address

0 (B_0x0): TIMx_CR1

1 (B_0x1): TIMx_CR2

2 (B_0x2): TIMx_SMCR
DBL

DMA burst length

0 (B_0x0): 1 transfer,

1 (B_0x1): 2 transfers,

2 (B_0x2): 3 transfers,

17 (B_0x11): 18 transfers.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32