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stm32 /stm32u0 /STM32U083 /EXTI /EXTI_IMR1

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Interpret as EXTI_IMR1

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https://regviz.com/r/stm32/stm32u0/STM32U073/EXTI/EXTI_IMR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)IM0 0 (B_0x0)IM1 0 (B_0x0)IM2 0 (B_0x0)IM3 0 (B_0x0)IM4 0 (B_0x0)IM5 0 (B_0x0)IM6 0 (B_0x0)IM7 0 (B_0x0)IM8 0 (B_0x0)IM9 0 (B_0x0)IM10 0 (B_0x0)IM11 0 (B_0x0)IM12 0 (B_0x0)IM13 0 (B_0x0)IM14 0 (B_0x0)IM15 0 (B_0x0)IM16 0 (B_0x0)IM17 0 (B_0x0)IM18 0 (B_0x0)IM19 0 (B_0x0)IM20 0 (B_0x0)IM21 0 (B_0x0)IM22 0 (B_0x0)IM23 0 (B_0x0)IM24 0 (B_0x0)IM25 0 (B_0x0)IM26 0 (B_0x0)IM27 0 (B_0x0)IM28 0 (B_0x0)IM29 0 (B_0x0)IM30 0 (B_0x0)IM31

IM11=B_0x0, IM26=B_0x0, IM28=B_0x0, IM15=B_0x0, IM9=B_0x0, IM27=B_0x0, IM6=B_0x0, IM14=B_0x0, IM23=B_0x0, IM4=B_0x0, IM3=B_0x0, IM18=B_0x0, IM21=B_0x0, IM30=B_0x0, IM5=B_0x0, IM31=B_0x0, IM16=B_0x0, IM12=B_0x0, IM17=B_0x0, IM22=B_0x0, IM24=B_0x0, IM1=B_0x0, IM25=B_0x0, IM13=B_0x0, IM8=B_0x0, IM29=B_0x0, IM0=B_0x0, IM2=B_0x0, IM10=B_0x0, IM7=B_0x0, IM20=B_0x0, IM19=B_0x0

Description

EXTI CPU wake-up with interrupt mask register

Fields

IM0

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM1

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM2

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM3

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM4

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM5

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM6

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM7

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM8

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM9

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM10

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM11

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM12

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM13

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM14

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM15

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM16

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM17

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM18

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM19

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM20

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM21

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM22

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM23

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM24

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM25

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM26

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM27

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM28

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM29

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM30

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked
IM31

CPU wake-up with interrupt mask on line x (x1=131 to 0) Setting/clearing each bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bits 18, 19, 22 and 26 are available only on STM32U0x3xx devices, they are reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt masked

1 (B_0x1): wake-up with interrupt unasked

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32