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stm32 /stm32u0 /STM32U083 /RCC /RCC_APBENR2

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Interpret as RCC_APBENR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SYSCFGEN 0 (B_0x0)TIM1EN 0 (B_0x0)SPI1EN 0 (B_0x0)USART1EN 0 (B_0x0)TIM15EN 0 (B_0x0)TIM16EN 0 (B_0x0)ADCEN

SPI1EN=B_0x0, USART1EN=B_0x0, TIM15EN=B_0x0, ADCEN=B_0x0, TIM16EN=B_0x0, TIM1EN=B_0x0, SYSCFGEN=B_0x0

Description

APB peripheral clock enable register 2

Fields

SYSCFGEN

SYSCFG, COMP and VREFBUF clock enable Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
TIM1EN

TIM1 timer clock enable Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
SPI1EN

SPI1 clock enable Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
USART1EN

USART1 clock enable Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
TIM15EN

TIM15 timer clock enable Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
TIM16EN

TIM16 timer clock enable Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
ADCEN

ADC clock enable Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32