Regviz

stm32 /stm32u0 /STM32U083 /TIM2 /TIM2_DCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TIM2_DCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32c0/STM32C071/TIM2/TIM2_DCR#0x0

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DBA0 (B_0x0)DBL

DBL=B_0x0, DBA=B_0x0

Description

TIM2 DMA control register

Fields

DBA

DMA base address

0 (B_0x0): TIMx_CR1

1 (B_0x1): TIMx_CR2

2 (B_0x2): TIMx_SMCR
DBL

DMA burst length

0 (B_0x0): 1 transfer,

1 (B_0x1): 2 transfers,

2 (B_0x2): 3 transfers,

17 (B_0x11): 18 transfers.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32