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stm32 /stm32u5 /STM32U535 /DBGMCU /APB1HFZR

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Interpret as APB1HFZR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_I2C4_STOP)DBG_I2C4_STOP 0 (DBG_LPTIM2_STOP)DBG_LPTIM2_STOP

Description

Debug MCU APB1H peripheral freeze register

Fields

DBG_I2C4_STOP

I2C4 stop in debug
DBG_LPTIM2_STOP

LPTIM2 stop in debug

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32