Regviz

stm32 /stm32u5 /STM32U535 /DCB /DSCSR

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Interpret as DSCSR

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https://regviz.com/r/stm32/stm32l5/STM32L552/DCB/DSCSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CDS)CDS

Description

Debug Security Control and Status Register

Fields

CDS

Current domain Secure

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32