Regviz

stm32 /stm32u5 /STM32U535 /FDCAN1_RAM /FDCAN_DBTP

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FDCAN_DBTP

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32h7/STM32H723/FDCAN1/FDCAN_DBTP#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DSJW0DTSEG20DTSEG10DBRP0 (TDC)TDC

Description

FDCAN Data Bit Timing and Prescaler Register

Fields

DSJW

Synchronization Jump Width
DTSEG2

Data time segment after sample point
DTSEG1

Data time segment after sample point
DBRP

Data BIt Rate Prescaler
TDC

Transceiver Delay Compensation

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32