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stm32 /stm32u5 /STM32U545 /DBGMCU /AHB3FZR

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Interpret as AHB3FZR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_LPDMA0_STOP)DBG_LPDMA0_STOP 0 (DBG_LPDMA1_STOP)DBG_LPDMA1_STOP 0 (DBG_LPDMA2_STOP)DBG_LPDMA2_STOP 0 (DBG_LPDMA3_STOP)DBG_LPDMA3_STOP

Description

Debug MCU AHB3 peripheral freeze register

Fields

DBG_LPDMA0_STOP

LPDMA channel 0 stop in debug
DBG_LPDMA1_STOP

LPDMA channel 1 stop in debug
DBG_LPDMA2_STOP

LPDMA channel 2 stop in debug
DBG_LPDMA3_STOP

LPDMA channel 3 stop in debug

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32