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stm32 /stm32u5 /STM32U545 /GTZC1_TZIC /SR2

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Interpret as SR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM1F)TIM1F 0 (SPI1F)SPI1F 0 (TIM8F)TIM8F 0 (USART1F)USART1F 0 (TIM15F)TIM15F 0 (TIM16F)TIM16F 0 (TIM17F)TIM17F 0 (SAI1F)SAI1F

Description

TZIC status register 2

Fields

TIM1F

illegal access flag for TIM1
SPI1F

illegal access flag for SPI1
TIM8F

illegal access flag for TIM8
USART1F

illegal access flag for USART1
TIM15F

illegal access flag for TIM5
TIM16F

illegal access flag for TIM6
TIM17F

illegal access flag for TIM7
SAI1F

illegal access flag for SAI1

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32