stm32 /stm32u5 /STM32U545 /I2C1 /CR2

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Interpret as CR2

31282724232019161512118743000000000000000000000000000000000000000000SADD0 (RD_WRN)RD_WRN0 (ADD10)ADD100 (HEAD10R)HEAD10R0 (START)START0 (STOP)STOP0 (NACK)NACK0NBYTES0 (RELOAD)RELOAD0 (AUTOEND)AUTOEND0 (PECBYTE)PECBYTE

Description

Control register 2

Fields

SADD

Slave address bit (master mode)

RD_WRN

Transfer direction (master mode)

ADD10

10-bit addressing mode (master mode)

HEAD10R

10-bit address header only read direction (master receiver mode)

START

Start generation

STOP

Stop generation (master mode)

NACK

NACK generation (slave mode)

NBYTES

Number of bytes

RELOAD

NBYTES reload mode

AUTOEND

Automatic end mode (master mode)

PECBYTE

Packet error checking byte

Links

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