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stm32 /stm32u5 /STM32U575 /MDF1 /CKGCR

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Interpret as CKGCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CKGDEN)CKGDEN 0 (CCK0EN)CCK0EN 0 (CCK1EN)CCK1EN 0 (CKGMOD)CKGMOD 0 (CCK0DIR)CCK0DIR 0 (CCK1DIR)CCK1DIR 0 (TRGSENS)TRGSENS 0TRGSRC0CCKDIV0PROCDIV0 (CKGACTIVE)CKGACTIVE

Description

MDF clock generator control register

Fields

CKGDEN

CKGDEN
CCK0EN

CCK0EN
CCK1EN

CCK1EN
CKGMOD

CKGMOD
CCK0DIR

CCK0DIR
CCK1DIR

CCK1DIR
TRGSENS

TRGSENS
TRGSRC

TRGSRC
CCKDIV

CCKDIV
PROCDIV

PROCDIV
CKGACTIVE

CKGACTIVE

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32