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stm32 /stm32u5 /STM32U575 /OCTOSPI1 /TCR

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Interpret as TCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DCYC0 (DHQC)DHQC 0 (SSHIFT)SSHIFT

Description

timing configuration register

Fields

DCYC

Number of dummy cycles
DHQC

Delay hold quarter cycle
SSHIFT

Sample shift

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32