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stm32 /stm32u5 /STM32U575 /PSSI /MIS

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Interpret as MIS

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https://regviz.com/r/stm32/stm32u5/STM32U535/PSSI/MIS#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OVR_MIS)OVR_MIS

Description

PSSI masked interrupt status register

Fields

OVR_MIS

OVR_MIS

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32