stm32 /stm32u5 /STM32U575 /PWR /PWR_DBPR

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Interpret as PWR_DBPR

31282724232019161512118743000000000000000000000000000000000000000000 (B_0x0)DBP

DBP=B_0x0

Description

PWR disable Backup domain register

Fields

DBP

Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers.

0 (B_0x0): Write access to Backup domain disabled

1 (B_0x1): Write access to Backup domain enabled

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