stm32 /stm32u5 /STM32U575 /RNG /CR

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Interpret as CR

31282724232019161512118743000000000000000000000000000000000000000000 (RNGEN)RNGEN0 (IE)IE0 (CED)CED0 (ARDIS)ARDIS0RNG_CONFIG30 (NISTC)NISTC0RNG_CONFIG20CLKDIV0RNG_CONFIG10 (CONDRST)CONDRST0 (CONFIGLOCK)CONFIGLOCK

Description

control register

Fields

RNGEN

True random number generator enable

IE

Interrupt Enable

CED

Clock error detection

ARDIS

Auto reset disable

RNG_CONFIG3

RNG configuration 3

NISTC

Non NIST compliant

RNG_CONFIG2

RNG configuration 2

CLKDIV

Clock divider factor

RNG_CONFIG1

RNG configuration 1

CONDRST

Conditioning soft reset

CONFIGLOCK

RNG Config Lock

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