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stm32 /stm32u5 /STM32U575 /RNG /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RNGEN)RNGEN 0 (IE)IE 0 (CED)CED 0 (ARDIS)ARDIS 0RNG_CONFIG3 0 (NISTC)NISTC 0RNG_CONFIG2 0CLKDIV0RNG_CONFIG10 (CONDRST)CONDRST 0 (CONFIGLOCK)CONFIGLOCK

Description

control register

Fields

RNGEN

True random number generator enable
IE

Interrupt Enable
CED

Clock error detection
ARDIS

Auto reset disable
RNG_CONFIG3

RNG configuration 3
NISTC

Non NIST compliant
RNG_CONFIG2

RNG configuration 2
CLKDIV

Clock divider factor
RNG_CONFIG1

RNG configuration 1
CONDRST

Conditioning soft reset
CONFIGLOCK

RNG Config Lock

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32