Regviz

stm32 /stm32u5 /STM32U585 /GTZC1_TZSC /TZSC_SECCFGR1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TZSC_SECCFGR1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32u5/STM32U575/GTZC1_TZSC/TZSC_SECCFGR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM2SEC)TIM2SEC 0 (TIM3SEC)TIM3SEC 0 (TIM4SEC)TIM4SEC 0 (TIM5SEC)TIM5SEC 0 (TIM6SEC)TIM6SEC 0 (TIM7SEC)TIM7SEC 0 (WWDGSEC)WWDGSEC 0 (IWDGSEC)IWDGSEC 0 (SPI2SEC)SPI2SEC 0 (USART2SEC)USART2SEC 0 (USART3SEC)USART3SEC 0 (UART4SEC)UART4SEC 0 (UART5SEC)UART5SEC 0 (I2C1SEC)I2C1SEC 0 (I2C2SEC)I2C2SEC 0 (CRSSEC)CRSSEC 0 (I2C4SEC)I2C4SEC 0 (LPTIM2SEC)LPTIM2SEC 0 (FDCAN1SEC)FDCAN1SEC 0 (UCPD1SEC)UCPD1SEC

Description

TZSC secure configuration register 1

Fields

TIM2SEC

secure access mode for TIM2
TIM3SEC

secure access mode for TIM3
TIM4SEC

secure access mode for TIM4
TIM5SEC

secure access mode for TIM5
TIM6SEC

secure access mode for TIM6
TIM7SEC

secure access mode for TIM7
WWDGSEC

secure access mode for WWDG
IWDGSEC

secure access mode for IWDG
SPI2SEC

secure access mode for SPI2
USART2SEC

secure access mode for USART2
USART3SEC

secure access mode for USART3
UART4SEC

secure access mode for UART4
UART5SEC

secure access mode for UART5
I2C1SEC

secure access mode for I2C1
I2C2SEC

secure access mode for I2C2
CRSSEC

secure access mode for CRS
I2C4SEC

secure access mode for I2C4
LPTIM2SEC

secure access mode for LPTIM2
FDCAN1SEC

secure access mode for FDCAN1
UCPD1SEC

secure access mode for UCPD1

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32