Regviz

stm32 /stm32u5 /STM32U585 /GTZC2_TZIC /SR1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SR1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32u5/STM32U575/GTZC2_TZIC/SR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI3F)SPI3F 0 (LPUART1F)LPUART1F 0 (I2C3F)I2C3F 0 (LPTIM1F)LPTIM1F 0 (LPTIM3F)LPTIM3F 0 (LPTIM4F)LPTIM4F 0 (OPAMPF)OPAMPF 0 (COMPF)COMPF 0 (ADC4F)ADC4F 0 (VREFBUFF)VREFBUFF 0 (DAC1F)DAC1F 0 (ADF1F)ADF1F

Description

TZIC status register 1

Fields

SPI3F

illegal access flag for SPI3
LPUART1F

illegal access flag for LPUART1
I2C3F

illegal access flag for I2C3
LPTIM1F

illegal access flag for LPTIM1
LPTIM3F

illegal access flag for LPTIM3
LPTIM4F

illegal access flag for LPTIM4
OPAMPF

illegal access flag for OPAMP
COMPF

illegal access flag for COMP
ADC4F

illegal access flag for ADC4
VREFBUFF

illegal access flag for VREFBUF
DAC1F

illegal access flag for DAC1
ADF1F

illegal access flag for ADF1

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32