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stm32 /stm32u5 /STM32U585 /SAI1 /AFRCR

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Interpret as AFRCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FRL0FSALL0 (FSDEF)FSDEF 0 (FSPOL)FSPOL 0 (FSOFF)FSOFF

Description

A frame configuration register

Fields

FRL

Frame length
FSALL

Frame synchronization active level length
FSDEF

Frame synchronization definition
FSPOL

Frame synchronization polarity
FSOFF

Frame synchronization offset

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32