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stm32 /stm32u5 /STM32U585 /TIM2 /ECR

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Interpret as ECR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IE)IE 0IDIR 0IBLK 0 (FIDX)FIDX 0IPOS 0PW0PWPRSC

Description

encoder control register

Fields

IE

Index enable
IDIR

Index direction
IBLK

Index blanking This bit indicates if the Index event is conditioned by the tim_ti3 input
FIDX

First index
IPOS

Index positioning
PW

Pulse width
PWPRSC

Pulse width prescaler

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32