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stm32 /stm32u5 /STM32U595 /DBGMCU /APB1LFZR

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Interpret as APB1LFZR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_TIM2_STOP)DBG_TIM2_STOP 0 (DBG_TIM3_STOP)DBG_TIM3_STOP 0 (DBG_TIM4_STOP)DBG_TIM4_STOP 0 (DBG_TIM5_STOP)DBG_TIM5_STOP 0 (DBG_TIM6_STOP)DBG_TIM6_STOP 0 (DBG_TIM7_STOP)DBG_TIM7_STOP 0 (DBG_WWDG_STOP)DBG_WWDG_STOP 0 (DBG_IWDG_STOP)DBG_IWDG_STOP 0 (DBG_I2C1_STOP)DBG_I2C1_STOP 0 (DBG_I2C2_STOP)DBG_I2C2_STOP

Description

Debug MCU APB1L peripheral freeze register

Fields

DBG_TIM2_STOP

TIM2 stop in debug
DBG_TIM3_STOP

TIM3 stop in debug
DBG_TIM4_STOP

TIM4 stop in debug
DBG_TIM5_STOP

TIM5 stop in debug
DBG_TIM6_STOP

TIM6 stop in debug
DBG_TIM7_STOP

TIM7 stop in debug
DBG_WWDG_STOP

Window watchdog counter stop in debug
DBG_IWDG_STOP

Independent watchdog counter stop in debug
DBG_I2C1_STOP

I2C1 SMBUS timeout stop in debug
DBG_I2C2_STOP

I2C2 SMBUS timeout stop in debug

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32