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stm32 /stm32u5 /STM32U595 /DBGMCU /APB3FZR

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Interpret as APB3FZR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_I2C3_STOP)DBG_I2C3_STOP 0 (DBG_LPTIM1_STOP)DBG_LPTIM1_STOP 0 (DBG_LPTIM3_STOP)DBG_LPTIM3_STOP 0 (DBG_LPTIM4_STOP)DBG_LPTIM4_STOP 0 (DBG_RTC_STOP)DBG_RTC_STOP

Description

Debug MCU APB3 peripheral freeze register

Fields

DBG_I2C3_STOP

I2C3 stop in debug
DBG_LPTIM1_STOP

LPTIM1 stop in debug
DBG_LPTIM3_STOP

LPTIM3 stop in debug
DBG_LPTIM4_STOP

LPTIM4 stop in debug
DBG_RTC_STOP

RTC stop in debug

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32