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stm32 /stm32u5 /STM32U595 /DBGMCU /CIDR2

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Interpret as CIDR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PREAMBLE

Description

Debug MCU CoreSight component identity register 2

Fields

PREAMBLE

component identification bits [23:16]

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32