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stm32 /stm32u5 /STM32U595 /DCACHE1 /DCACHE_CR

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Interpret as DCACHE_CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EN)EN 0 (CACHEINV)CACHEINV 0CACHECMD 0 (STARTCMD)STARTCMD 0 (RHITMEN)RHITMEN 0 (RMISSMEN)RMISSMEN 0 (RHITMRST)RHITMRST 0 (RMISSMRST)RMISSMRST 0 (WHITMEN)WHITMEN 0 (WMISSMEN)WMISSMEN 0 (WHITMRST)WHITMRST 0 (WMISSMRST)WMISSMRST 0 (HBURST)HBURST

Description

DCACHE control register

Fields

EN

EN
CACHEINV

CACHEINV
CACHECMD

CACHECMD
STARTCMD

STARTCMD
RHITMEN

RHITMEN
RMISSMEN

RMISSMEN
RHITMRST

RHITMRST
RMISSMRST

RMISSMRST
WHITMEN

WHITMEN
WMISSMEN

WMISSMEN
WHITMRST

WHITMRST
WMISSMRST

WMISSMRST
HBURST

HBURST

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32