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stm32 /stm32u5 /STM32U595 /FMC /BWTR1

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Interpret as BWTR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADDSET0ADDHLD0DATAST0BUSTURN0ACCMOD 0DATAHLD

Description

SRAM/NOR-Flash write timing registers 1

Fields

ADDSET

Address setup phase duration
ADDHLD

Address-hold phase duration
DATAST

Data-phase duration
BUSTURN

Bus turnaround phase duration
ACCMOD

Access mode
DATAHLD

Data hold phase duration

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32