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stm32 /stm32u5 /STM32U595 /OCTOSPI1 /HLCR

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Interpret as HLCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LM)LM 0 (WZL)WZL 0TACC0TRWR

Description

HyperBus latency configuration register

Fields

LM

Latency mode
WZL

Write zero latency
TACC

Access time
TRWR

Read write recovery time

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32