Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/stm32/stm32l5/STM32L552/TIM3/CNT#0x0
counter
Least significant part of counter value
Most significant part counter value (on TIM2 and TIM5)
Most significant bit of counter value (on TIM2 and TIM5)
https://github.com/modm-io/cmsis-svd-stm32