Regviz

stm32 /stm32u5 /STM32U5A5 /TIM16 /OR1

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Interpret as OR1

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https://regviz.com/r/stm32/stm32u5/STM32U535/TIM16/OR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HSE32EN)HSE32EN

Description

option register 1

Fields

HSE32EN

HSE Divided by 32 enable

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32