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stm32 /stm32u5 /STM32U5A9 /DCMI /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HSYNC)HSYNC 0 (VSYNC)VSYNC 0 (FNE)FNE

Description

status register

Fields

HSYNC

Horizontal synchronization
VSYNC

Vertical synchronization
FNE

FIFO not empty

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32