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stm32 /stm32u5 /STM32U5A9 /FDCAN1_RAM /FDCAN_IR

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Interpret as FDCAN_IR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RF0N)RF0N 0 (RF0F)RF0F 0 (RF0L)RF0L 0 (RF1N)RF1N 0 (RF1F)RF1F 0 (RF1L)RF1L 0 (HPM)HPM 0 (TC)TC 0 (TCF)TCF 0 (TFE)TFE 0 (TEFN)TEFN 0 (TEFF)TEFF 0 (TEFL)TEFL 0 (TSW)TSW 0 (MRAF)MRAF 0 (TOO)TOO 0 (ELO)ELO 0 (EP)EP 0 (EW)EW 0 (BO)BO 0 (WDI)WDI 0 (PEA)PEA 0 (PED)PED 0 (ARA)ARA

Description

FDCAN Interrupt Register

Fields

RF0N

RF0N
RF0F

RF0F
RF0L

RF0L
RF1N

RF1N
RF1F

RF1F
RF1L

RF1L
HPM

HPM
TC

TC
TCF

TCF
TFE

TFE
TEFN

TEFN
TEFF

TEFF
TEFL

TEFL
TSW

TSW
MRAF

MRAF
TOO

TOO
ELO

ELO
EP

EP
EW

EW
BO

BO
WDI

WDI
PEA

PEA
PED

PED
ARA

ARA

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32