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stm32 /stm32u5 /STM32U5A9 /FMAC /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RIEN)RIEN 0 (WIEN)WIEN 0 (OVFLIEN)OVFLIEN 0 (UNFLIEN)UNFLIEN 0 (SATIEN)SATIEN 0 (DMAREN)DMAREN 0 (DMAWEN)DMAWEN 0 (CLIPEN)CLIPEN 0 (RESET)RESET

Description

FMAC Control register

Fields

RIEN

Enable read interrupt
WIEN

Enable write interrupt
OVFLIEN

Enable overflow error interrupts
UNFLIEN

Enable underflow error interrupts
SATIEN

Enable saturation error interrupts
DMAREN

Enable DMA read channel requests
DMAWEN

Enable DMA write channel requests
CLIPEN

Enable clipping
RESET

Reset FMAC unit

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32