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stm32 /stm32u5 /STM32U5A9 /GTZC1_MPCBB1 /MPCBB1_CFGLOCK2

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Interpret as MPCBB1_CFGLOCK2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPLCK32)SPLCK32 0 (SPLCK33)SPLCK33 0 (SPLCK34)SPLCK34 0 (SPLCK35)SPLCK35 0 (SPLCK36)SPLCK36 0 (SPLCK37)SPLCK37 0 (SPLCK38)SPLCK38 0 (SPLCK39)SPLCK39 0 (SPLCK40)SPLCK40 0 (SPLCK41)SPLCK41 0 (SPLCK42)SPLCK42 0 (SPLCK43)SPLCK43 0 (SPLCK44)SPLCK44 0 (SPLCK45)SPLCK45 0 (SPLCK46)SPLCK46 0 (SPLCK47)SPLCK47 0 (SPLCK48)SPLCK48 0 (SPLCK49)SPLCK49 0 (SPLCK50)SPLCK50 0 (SPLCK51)SPLCK51

Description

GTZC1 SRAMz MPCBB configuration lock register 2

Fields

SPLCK32

SPLCK32
SPLCK33

SPLCK33
SPLCK34

SPLCK34
SPLCK35

SPLCK35
SPLCK36

SPLCK36
SPLCK37

SPLCK37
SPLCK38

SPLCK38
SPLCK39

SPLCK39
SPLCK40

SPLCK40
SPLCK41

SPLCK41
SPLCK42

SPLCK42
SPLCK43

SPLCK43
SPLCK44

SPLCK44
SPLCK45

SPLCK45
SPLCK46

SPLCK46
SPLCK47

SPLCK47
SPLCK48

SPLCK48
SPLCK49

SPLCK49
SPLCK50

SPLCK50
SPLCK51

SPLCK51

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32