Regviz

stm32 /stm32u5 /STM32U5A9 /OTG_HS /GOTGCTL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as GOTGCTL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32u5/STM32U575/OTG_FS/GOTGCTL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SRQSCS)SRQSCS 0 (SRQ)SRQ 0 (VBVALOEN)VBVALOEN 0 (VBVALOVAL)VBVALOVAL 0 (AVALOEN)AVALOEN 0 (AVALOVAL)AVALOVAL 0 (BVALOEN)BVALOEN 0 (BVALOVAL)BVALOVAL 0 (HNGSCS)HNGSCS 0 (HNPRQ)HNPRQ 0 (HSHNPEN)HSHNPEN 0 (DHNPEN)DHNPEN 0 (EHEN)EHEN 0 (CIDSTS)CIDSTS 0 (DBCT)DBCT 0 (ASVLD)ASVLD 0 (BSVLD)BSVLD 0 (OTGVER)OTGVER 0 (CURMOD)CURMOD

Description

The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.

Fields

SRQSCS

SRQSCS
SRQ

SRQ
VBVALOEN

VBVALOEN
VBVALOVAL

VBVALOVAL
AVALOEN

AVALOEN
AVALOVAL

AVALOVAL
BVALOEN

BVALOEN
BVALOVAL

BVALOVAL
HNGSCS

HNGSCS
HNPRQ

HNPRQ
HSHNPEN

HSHNPEN
DHNPEN

DHNPEN
EHEN

EHEN
CIDSTS

CIDSTS
DBCT

DBCT
ASVLD

ASVLD
BSVLD

BSVLD
OTGVER

OTGVER
CURMOD

CURMOD

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32