stm32 /stm32u5 /STM32U5A9 /SAI1 /ACR1

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Interpret as ACR1

31282724232019161512118743000000000000000000000000000000000000000000MODE0PRTCFG0DS0 (LSBFIRST)LSBFIRST0 (CKSTR)CKSTR0SYNCEN0 (MONO)MONO0 (OUTDRIV)OUTDRIV0 (SAIAEN)SAIAEN0 (DMAEN)DMAEN0 (NODIV)NODIV0MCKDIV0 (OSR)OSR0 (MCKEN)MCKEN

Description

A Configuration register 1

Fields

MODE

Audio block mode

PRTCFG

Protocol configuration

DS

Data size

LSBFIRST

Least significant bit first

CKSTR

Clock strobing edge

SYNCEN

Synchronization enable

MONO

Mono mode

OUTDRIV

Output drive

SAIAEN

Audio block A enable

DMAEN

DMA enable

NODIV

No divider

MCKDIV

Master clock divider

OSR

OSR

MCKEN

MCKEN

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