clock control register
| CLKDIV | Clock divide factor |
| PWRSAV | Power saving configuration bit |
| WIDBUS | Wide bus mode enable bit |
| NEGEDGE | SDIO_CK dephasing selection bit |
| HWFC_EN | HW Flow Control enable |
| DDR | Data rate signaling selection |
| BUSSPEED | Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50, SDR104 |
| SELCLKRX | Receive clock selection |