stm32 /stm32u5 /STM32U5A9 /SPI1 /CFG1

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Interpret as CFG1

31282724232019161512118743000000000000000000000000000000000000000000DSIZE0FTHVL0 (UDRCFG)UDRCFG0 (RXDMAEN)RXDMAEN0 (TXDMAEN)TXDMAEN0CRCSIZE0 (CRCEN)CRCEN0MBR0 (BPASS)BPASS

Description

configuration register 1

Fields

DSIZE

Number of bits in at single SPI data frame

FTHVL

threshold level

UDRCFG

Behavior of slave transmitter at underrun condition

RXDMAEN

Rx DMA stream enable

TXDMAEN

Tx DMA stream enable

CRCSIZE

Length of CRC frame to be transacted and compared

CRCEN

Hardware CRC computation enable

MBR

Master baud rate

BPASS

BPASS

Links

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