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stm32 /stm32u5 /STM32U5Fx /ADF1 /ADF_DFLT0CR

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Interpret as ADF_DFLT0CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DFLTEN)DFLTEN 0 (DMAEN)DMAEN 0 (FTH)FTH 0ACQMOD 0TRGSRC0NBDIS0 (DFLTRUN)DFLTRUN 0 (DFLTACTIVE)DFLTACTIVE

Description

ADF digital filter control register 0

Fields

DFLTEN

DFLT0 enable
DMAEN

DMA requests enable
FTH

RXFIFO threshold selection
ACQMOD

DFLT0 trigger mode
TRGSRC

DFLT0 trigger signal selection
NBDIS

Number of samples to be discarded
DFLTRUN

DFLT0 run status flag
DFLTACTIVE

DFLT0 active flag

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32