CKE=B_0x0, DEN=B_0x0
DSI Host PHY control register
| DEN | Digital enable When set to 0, this bit places the digital section of the D-PHY in the reset state 0 (B_0x0): The digital section of the D-PHY is in the reset state. 1 (B_0x1): The digital section of the D-PHY is enabled. |
| CKE | Clock enable This bit enables the D-PHY clock lane module: 0 (B_0x0): D-PHY clock lane module is disabled. 1 (B_0x1): D-PHY clock lane module is enabled. |