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stm32 /stm32u5 /STM32U5Fx /FMC /PCR

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Interpret as PCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PWAITEN)PWAITEN 0 (PBKEN)PBKEN 0 (PTYP)PTYP 0PWID 0 (ECCEN)ECCEN 0TCLR0TAR0ECCPS

Description

NAND Flash control registers

Fields

PWAITEN

Wait feature enable bit
PBKEN

NAND Flash memory bank enable bit
PTYP

Memory type
PWID

Data bus width
ECCEN

ECC computation logic enable bit
TCLR

CLE to RE delay
TAR

ALE to RE delay
ECCPS

ECC page size

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32