Regviz

stm32 /stm32u5 /STM32U5Fx /HASH /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DINIS)DINIS 0 (DCIS)DCIS 0 (DMAS)DMAS 0 (BUSY)BUSY 0NBWP0 (DINNE)DINNE 0NBWE

Description

status register

Fields

DINIS

Data input interrupt status
DCIS

Digest calculation completion interrupt status
DMAS

DMA Status
BUSY

Busy bit
NBWP

Number of words already pushed
DINNE

DIN not empty
NBWE

Number of words expected

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32