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stm32 /stm32u5 /STM32U5Gx /DCACHE1 /DCACHE_IER

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Interpret as DCACHE_IER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BSYENDIE)BSYENDIE 0 (ERRIE)ERRIE 0 (CMDENDIE)CMDENDIE

Description

DCACHE interrupt enable register

Fields

BSYENDIE

BSYENDIE
ERRIE

ERRIE
CMDENDIE

CMDENDIE

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32