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stm32 /stm32u5 /STM32U5Gx /DLYBOS1 /DLYB_CR

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Interpret as DLYB_CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DEN)DEN 0 (SEN)SEN

Description

control register

Fields

DEN

Operational amplifier Enable
SEN

OPALPM

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32