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stm32 /stm32u5 /STM32U5Gx /DMA2D /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (START)START 0 (SUSP)SUSP 0 (ABORT)ABORT 0 (LOM)LOM 0 (TEIE)TEIE 0 (TCIE)TCIE 0 (TWIE)TWIE 0 (CAEIE)CAEIE 0 (CTCIE)CTCIE 0 (CEIE)CEIE 0MODE

Description

control register

Fields

START

Start
SUSP

Suspend
ABORT

Abort
LOM

Line Offset Mode
TEIE

Transfer error interrupt enable
TCIE

Transfer complete interrupt enable
TWIE

Transfer watermark interrupt enable
CAEIE

CLUT access error interrupt enable
CTCIE

CLUT transfer complete interrupt enable
CEIE

Configuration Error Interrupt Enable
MODE

DMA2D mode

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32